1. Field of the Invention
The present invention relates to floating point units and, more particularly, but not by way of limitation, to a method and apparatus for sticky and leading one detection.
2. Description of the Related Art
Floating point units perform various arithmetic operations such as addition, subtraction, multiplication, division, square root on numerical operands represented in floating point notation. Floating point notation utilizes the format of a sign, a mantissa, and an exponent to represent a number. Floating point units recognize floating point numbers because floating point numbers include a predetermined bit field with the sign, mantissa, and exponent each occupying the same bit positions regardless of the sign and magnitude of the actual number. Thus, a floating point unit ascertains the sign, mantissa, and exponent for any input floating point number by decoding bit positions and then determining the sign, the numeric value of the mantissa, and the magnitude of the exponent from the decoded bits representing the floating point number.
The IEEE promulgates standards (specifically the ANSI/IEEE 754-1985) that govern the representation of numbers in floating point notation to ensure uniformity among floating point notation users. The IEEE standards include extended, double, and single precision formats. Denormalized formats are also included in the standard but will not be discussed in relation to this invention. Those formats determine the quantity of significant figures or size of the bit field for any number represented in floating point notation. For example, a double precision format defines 64 bits for operands with one bit representing the sign, eleven bits representing the magnitude of the exponent, and 52 bits representing the numeric value of the mantissa. Alternatively, a single precision format defines 32 bits for operands with one bit representing the sign, 8 bits representing the magnitude of the exponent, and 23 bits representing the numeric value of the mantissa.
Regardless of the particular floating point notation format utilized, the IEEE standard demands the normalization of the mantissa for all operands as well as any results from an arithmetic operation performed on the operands. Normalization of a floating point number requires the leading one in the mantissa always be placed to the left of the decimal point with the magnitude of the exponent adjusted accordingly. Consequently, the IEEE standard places the leading one in the most significant bit of the mantissa bit field so that the leading one appears not included and is referred to as a "hidden" bit. Accordingly, in double precision format, the mantissa bit field actually constitutes 53 bits with the leading one "hidden", while in single precision format, the mantissa bit field actually constitutes 24 bits with the leading one "hidden".
Due to IEEE standards requiring normalization of a mantissa, floating point numbers rarely have equal exponents. Accordingly, when floating point units add or subtract a second operand represented in floating point notation with a first operand represented in floating point notation, the mantissa of the second operand typically must be shifted because an addition or subtraction cannot be performed until the exponent of the second operand equals the exponent of the first operand. The floating point units equalize the first and second exponents by shifting the mantissa of the second operand relative to the mantissa of the first operand. Shifting the second mantissa to the right increases its exponent one for each shift, while shifting the second mantissa to the left decreases its exponent one for each shift.
Floating point units typically include a comparator and alignment shifter for shifting the second mantissa such that the second exponent equals the first exponent. The comparator compares the values of the first and second exponents to determine the number of shifts the second mantissa requires to equalize the first and second exponents. After determining an alignment shift value, the comparator controls the alignment shifter in accordance with the alignment shift value to shift the second mantissa relative to the first mantissa.
The alignment shifter includes a bit field greater than the bit field for the first mantissa in order to accommodate any bits of the second mantissa not aligned with the bits of the first mantissa. The first and second mantissas will not align whenever there exists a difference in magnitude between the first and second exponent. Specifically, if the second exponent exceeds the first exponent, at least one bit of the second mantissa will reside within the alignment shifter in a bit positions left of the most significant bit of the first mantissa (hereinafter referred to as second path bits). Conversely, if the second exponent is less than the first exponent, at least one bit of the second mantissa will reside in bit positions to the right of the least significant bit of the first mantissa (hereinafter referred to as sticky bits).
Floating point units include an adder that performs the desired operation (i.e., addition or subtraction) on the first mantissa and any bits of the second mantissa residing in bit positions aligned with the bits of the first mantissa to produce an intermediate result. The output from the adder forms an intermediate result because the final result of the operation must be modified if the shifting of the second mantissa created second path bits. If second path bits exist, the intermediate result must be modified by placing the least significant bit of the second path bits in the bit position to the left of the most significant bit of the intermediate result so that the final result reflects all the bits of the second mantissa.
Floating point units include a normalize shifter that normalizes the final result by shifting the leading one of the final result until it resides to the left of the most significant bit of the normalize shifter. However, before the normalize shifter can normalize the final result, a normalize shift value must be calculated from the position of the leading one within the second path bits. Consequently, floating point units include a leading ones detector (LOD) that inputs the second path bits, determines the position of the leading one, and calculates the normalize shift value required to control the normalize shifter.
Floating point units include an adjust circuit that will supply the final sign, exponent and mantissa required for IEEE correct results.
If the first exponent exceeds the second exponent, sticky bits rather than second path bits exist. Consequently, the intermediate result output from the adder does not require modification and, thus, forms the final result. A leading ones detector (LOD) similar to the LOD described above determines the leading one within the intermediate result and calculates a normalize shift value accordingly. Normalize shifter normalizes the unmodified final result and then outputs a normalized final result to the adjust circuit.
The adjust circuit rounds off the final result utilizing the sticky bits. Accordingly, floating point units include a sticky bit detector that detects sticky bits and then outputs them to the adjust circuit.
A sticky bit detector typically detects each shift performed by the alignment shifter and then compares the actual number of shifts performed with the number of reference shifts required to place the least significant bit of the second mantissa aligned with the least significant bit of the first mantissa. If the number of actual shifts exceeds the number of reference shifts, then sticky bits exist, and the difference between the actual number of shifts and the reference shifts indicates the number of sticky bits.
After detecting the sticky bits, the sticky bit detector outputs the sticky bits to the adjust circuit. The adjust circuit inputs the sticky bits and utilizes the sticky bit or bits to form the final answer. Finally, the adjust circuit associates the proper exponent and sign with the final mantissa and outputs the final mantissa, sign, and exponent as the final answer.
Although the above sticky bit detector and LOD for second path bits operate adequately, their implementation in separate circuitry unnecessarily increases the size of floating point units. Furthermore, the utilization of separate circuitry increases the number of steps a floating point unit must perform during an operation which slows the operating speed of the floating point unit. Additional steps slow the operating speed of the floating point unit because each additional step requires at least one separate clock cycle. Accordingly, because floating point units iteratively perform multiple operations, separately detecting sticky bits and a leading one in the second path bits significantly increases the time required to complete a series of operations.
A consequence of the slowed operating speed beyond simple inefficiency is that floating point units implemented with the separate circuitry cannot be utilized with high speed circuitry. For example, circuitry operating at high frequencies would require a result from a floating point unit at a time before an operation has been finished. That is, the additional clock cycles required to perform both detection steps slow the floating point unit to a level where it cannot perform arithmetic operations quickly enough to satisfy the demands of high speed circuitry.
Accordingly, circuitry that eliminates the separate detection of sticky bits and second path bits would reduce the amount of hardware and increase the speed of any floating point unit so that it could be utilized with high speed circuitry.